The next generation of intelligent and autonomous systems requires not only novel devices but also new silicon architectures and design workflows that transcend conventional approaches to deliver real-time learning, perception, and decision-making under severe power and resource constraints. In this talk, I will outline a cross-layer methodology for architecting silicon for embodied AI, from workload characterization and benchmarking to architecture exploration, compiler integration, and system prototyping. Central to this effort are compute-in-memory accelerators, mixed-signal neuromorphic architectures, and memory-centric SoCs that integrate hybrid RRAM/SRAM arrays, all designed within workflow frameworks that couple algorithmic needs with hardware capabilities. Case studies will highlight reconfigurable streaming-dataflow architectures for reasoning and decision-making, heterogeneous SoCs optimized for autonomous workloads, and bio-mimetic silicon platforms for navigation and planning. By unifying design flows, benchmarking, and circuit innovation, this work illustrates how silicon architectures can be systematically engineered to achieve the transparency, energy efficiency, and adaptability demanded by embodied intelligence and autonomy.