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BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Penn Engineering Events - ECPv6.18.0//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Penn Engineering Events X-ORIGINAL-URL:https://seasevents.nmsdev7.com X-WR-CALDESC:Events for Penn Engineering Events REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20190310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20191103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20200308T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20201101T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20210314T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20211107T060000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/New_York:20201113T150000 DTEND;TZID=America/New_York:20201113T160000 DTSTAMP:20201030T171328Z CREATED:20201030T171328Z LAST-MODIFIED:20201030T171328Z UID:3627-1605279600-1605283200@seasevents.nmsdev7.com SUMMARY:MEAM Ph.D. Thesis Defense: “All-Passive Hardware Architectures for Neuromorphic Computation” DESCRIPTION:Human brains demonstrate how simple computational primitives can be combined in massively parallel ways to produce networks capable of identifying complicated patterns in sensory data. In contrast\, electronic computers adopt hardware architectures that process information serially\, leading to higher latency and power consumption when implementing intrinsically parallel algorithms\, such as neural networks. This software-hardware architectural mismatch has acquired greater attention due to the widespread adoption of large neural networks and has encouraged the prospect of specialized neuromorphic computers. There is great interest in low latency analog neuromorphic designs that utilize passive crossbar arrays to accomplish the dual tasks of storing synaptic weights and computing dot products. Although this compute-in-memory paradigm promises high circuit density and 3D integrability\, prevalent implementations combine them with crossbar-incompatible CMOS neurons\, a paring that impedes overall system scalability. This thesis addresses the scalability bottleneck by evolving fully crossbar – compatible neuromorphic architectures based on passive circuit embodiments of neuron and synapses. \nWe demonstrate via SPICE circuit simulations how a shallow network of diode-resistor based passive neurons and resistive voltage summers\, despite its inherent inability to buffer\, amplify and invert signals\, can recognize MNIST digits with 95.4% accuracy. We introduce weight-to-conductance mappings that enable resource-efficient implementation of negative weights. The performance impacts of nanoscale defects are evaluated and methods to boost fault-tolerance are proposed. Compared with conventional implementations\, we find all-passive neuromorphic hardware promise higher speed\, smaller footprints\, and improved vertical scalability. URL:https://seasevents.nmsdev7.com/event/meam-ph-d-thesis-defense-all-passive-hardware-architectures-for-neuromorphic-computation/ LOCATION:Zoom – Email MEAM for Link\, peterlit@seas.upenn.edu CATEGORIES:Seminar,Dissertation or Thesis Defense ORGANIZER;CN="Mechanical Engineering and Applied Mechanics":MAILTO:meam@seas.upenn.edu END:VEVENT END:VCALENDAR