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SUMMARY:ESE Spring Seminar - "The Next Leap in Hardware Systems: Powered by Heterogenous Memory\, Logic\, and 3D Integration"
DESCRIPTION:Computing is at a critical juncture. Applications such as AI/ML demand much larger memory\, higher bandwidth\, and lower-energy compute compared to business as usual. New hardware systems\, powered by heterogenous memory\, logic\, and 3D integration\, are required for large energy efficiency\, throughput\, and scaleup benefits. I will present my contributions to three such heterogeneous systems: \n\nThe first edge AI/ML chips with full on-chip inference and training of CNNs and Transformers using foundry Resistive RAM (RRAM). The heterogeneous combination of RRAM and SRAM enables new circuit-architecture-algorithm interplay\, resulting in 9× or higher end-to-end Energy-Delay-Product (EDP) benefits versus traditional duty-cycled systems using SRAM\, DRAM\, or Flash.\nNew multi-chip Illusion systems for scaleup to 16× larger AI/ML models with 11× or higher EDP benefits versus traditional systems. Illusion minimizes inter-chip traffic by co-optimizing per-chip memory size\, heterogeneous inter- and intra-chip interconnects\, and idle power via fine-grained power management\, thus creating the illusion (within 10% EDP) of a Dream Chip with all resources on-chip.\nThe first foundry heterogeneous monolithic 3D hardware integrating silicon CMOS\, carbon nanotube field-effect transistors and RRAM\, demonstrating 4× memory bandwidth versus iso-footprint\, apples-to-apples conventional designs. Such benefits are only possible through new 3D architectures instead of 3D physical design alone.\n\nBigger benefits can be obtained for a wide set of applications by such hardware systems powered by a wider set of heterogeneous technologies. These also create exciting avenues for new courses.
URL:https://seasevents.nmsdev7.com/event/ese-spring-seminar-tbd-8/
LOCATION:Towne 337
CATEGORIES:Colloquium
ORGANIZER;CN="Electrical and Systems Engineering":MAILTO:eseevents@seas.upenn.edu
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