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BEGIN:VCALENDAR VERSION:2.0 PRODID:-//Penn Engineering Events - ECPv6.18.0//NONSGML v1.0//EN CALSCALE:GREGORIAN METHOD:PUBLISH X-WR-CALNAME:Penn Engineering Events X-ORIGINAL-URL:https://seasevents.nmsdev7.com X-WR-CALDESC:Events for Penn Engineering Events REFRESH-INTERVAL;VALUE=DURATION:PT1H X-Robots-Tag:noindex X-PUBLISHED-TTL:PT1H BEGIN:VTIMEZONE TZID:America/New_York BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20180311T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20181104T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20190310T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20191103T060000 END:STANDARD BEGIN:DAYLIGHT TZOFFSETFROM:-0500 TZOFFSETTO:-0400 TZNAME:EDT DTSTART:20200308T070000 END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0400 TZOFFSETTO:-0500 TZNAME:EST DTSTART:20201101T060000 END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTART;TZID=America/New_York:20190314T110000 DTEND;TZID=America/New_York:20190314T120000 DTSTAMP:20190225T153553Z CREATED:20190225T153553Z LAST-MODIFIED:20190225T153553Z UID:1388-1552561200-1552564800@seasevents.nmsdev7.com SUMMARY:ESE Seminar: "Software\, Architecture\, and VLSI Co-Design for Efficient Task-Based Parallel Runtimes" DESCRIPTION:Fast-paced changes across the computing stack are creating opportunities for innovation by bridging software\, architecture\, and VLSI. Cross-cutting research is challenging\, but it can expose key insights that would otherwise be hidden by abstractions. In this talk\, I will demonstrate a cross-stack approach to improve the efficiency of task-based parallel runtimes\, which are important because they underpin the parallelization of state-of-the-art graph analytics and machine learning frameworks. Shifting the focus downward\, I will discuss a cross-stack approach that addresses key circuit-level challenges in integrated voltage regulation. To finish the talk\, I will discuss my future plans to apply a cross-stack research approach to expand beyond the perceived limits of intelligence on the edge and also to decrease the challenges of complex ASIC design with hardware design techniques based on Lego-like tiling. URL:https://seasevents.nmsdev7.com/event/ese-seminar-software-architecture-and-vlsi-co-design-for-efficient-task-based-parallel-runtimes/ LOCATION:Room 337\, Towne Building\, 220 South 33rd Street\, Philadelphia\, PA\, 19104\, United States ORGANIZER;CN="Electrical and Systems Engineering":MAILTO:eseevents@seas.upenn.edu END:VEVENT END:VCALENDAR