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DTSTART;TZID=America/New_York:20210304T110000
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CREATED:20210211T142929Z
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UID:4219-1614855600-1614859200@seasevents.nmsdev7.com
SUMMARY:ESE Seminar: "High-Level Synthesis of Dynamically Scheduled Circuits"
DESCRIPTION:The slowdown in transistor scaling and the end of Moore’s law indicate a need to invest in new computing paradigms; specialized hardware devices\, such as FPGAs and ASICs\, are a promising solution as they can achieve high processing capabilities and energy efficiency. However\, a major barrier to the global success of specialized computing is the difficulty of hardware design. High-level synthesis (HLS) tools generate digital hardware designs from high-level programming languages (e.g.\, C/C++) and promise to liberate designers from low-level hardware description details. Yet\, HLS tools are still acceptable only for certain classes of applications and criticized for the difficulty of extracting the desired level of performance: generating good circuits still requires tedious code restructuring and hardware design expertise. \nIn this talk\, I will present a new HLS methodology that produces dynamically scheduled\, dataflow circuits out of C/C++ code; the resulting circuits achieve good performance out-of-the-box and realize behaviors that are beyond the capabilities of standard HLS tools. I will describe mathematical models to optimize the performance and area of the resulting circuits\, as well as techniques to achieve characteristics that standard HLS cannot support\, such as out-of-order memory accesses and speculative execution. These contributions redefine the HLS paradigm by introducing characteristics of modern superscalar processors to hardware designs; such behaviors are key for specialized computing to be successful in new contexts and broader application domains.
URL:https://seasevents.nmsdev7.com/event/ese-seminar-high-level-synthesis-of-dynamically-scheduled-circuits/
LOCATION:Zoom – Email ESE for Link jbatter@seas.upenn.edu
CATEGORIES:Seminar,Faculty,Colloquium,Student
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