BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//Penn Engineering Events - ECPv6.16.3//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-WR-CALNAME:Penn Engineering Events
X-ORIGINAL-URL:https://seasevents.nmsdev7.com
X-WR-CALDESC:Events for Penn Engineering Events
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:America/New_York
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20230312T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20231105T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20240310T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20241103T060000
END:STANDARD
BEGIN:DAYLIGHT
TZOFFSETFROM:-0500
TZOFFSETTO:-0400
TZNAME:EDT
DTSTART:20250309T070000
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0400
TZOFFSETTO:-0500
TZNAME:EST
DTSTART:20251102T060000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=America/New_York:20241126T110000
DTEND;TZID=America/New_York:20241126T130000
DTSTAMP:20260602T220113
CREATED:20241114T141201Z
LAST-MODIFIED:20241114T141201Z
UID:12615-1732618800-1732626000@seasevents.nmsdev7.com
SUMMARY:ESE PhD Thesis Defense: "Software-like Incremental Refinement on FPGA using Partial Reconfiguration"
DESCRIPTION:To improve FPGA design productivity\, our goal is to create a development experience for FPGAs that aligns closely with widely accepted software design principles. Software programmers quickly test their minimally completed design\, identify the bottleneck\, and incrementally refine the design. In FPGA design\, however\, such incremental refinement is not currently supported. (1) FPGA compilation is long\, (2) a minor refinement leads to another long compilation\, and (3) FPGA developers cannot easily identify a bottleneck of the design to know where to focus optimization effort to improve the application execution time. We introduce a divide-and-conquer strategy in FPGA compilation\, proposing a fast separate FPGA compilation using a Network-on-Chip (NoC) and Partial Reconfiguration (PR). Building upon this separate compilation framework\, in this thesis\, we take the next step to support variable-sized pages using Hierarchical PR to provide flexibility to the users. With variable-sized pages\, users can quickly test the design on the hardware\, just like software programmers start from a barely functional design. In addition\, we propose a bottleneck identification scheme based on FIFO counters to provide profiling capability in FPGA design. Finally\, we introduce a fast incremental refinement strategy that integrates our fast compilation framework and bottleneck identification scheme. The idea is to quickly map the design on the FPGA using the fast compilation framework and incrementally refine the design based on our bottleneck identification. The fast compilation with the NoC and PR pages iterates many initial yet important design points quickly\, and for the final\, optimized design\, our strategy migrates to the monolithic system that does not have the area and bandwidth overhead of the NoC. Throughout the design tuning\, we always have a hardware-mapped design whose performance we can measure to provide feedback to the users or automation script to identify the next bottleneck. We evaluate our fast incremental strategy with design tuning for realistic High Level Synthesis applications. Our framework\, fully compatible with AMD Vitis\, achieves 1.3–2.7× faster tuning time than a monolithic flow where the vendor tool monolithically compiles each design point.
URL:https://seasevents.nmsdev7.com/event/ese-phd-thesis-defense-software-like-incremental-refinement-on-fpga-using-partial-reconfiguration/
LOCATION:Raisler Lounge (Room 225)\, Towne Building\, 220 South 33rd Street\, Philadelphia\, PA\, 19104\, United States
CATEGORIES:Dissertation or Thesis Defense
ORGANIZER;CN="Electrical and Systems Engineering":MAILTO:eseevents@seas.upenn.edu
END:VEVENT
END:VCALENDAR