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DTSTART;TZID=America/New_York:20201006T110000
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DTSTAMP:20260407T111440
CREATED:20200918T010946Z
LAST-MODIFIED:20200918T010946Z
UID:3452-1601982000-1601985600@seasevents.nmsdev7.com
SUMMARY:ESE Grace Hopper Lecture: "Emerging Non-Volatile Ferroelectric Memory"
DESCRIPTION:Abstract\nThe last decade has seen a remarkable shift in usage and value of semiconductor memory technologies. These changes are driven by the elevation of four particular target applications –(1) mobile multi-media applications\, (2) explosive growth in the sheer volume of data that is being created and stored\, (3) emphasis from the individual components to the configurability in high-volume subsystems and (4) applications in brain inspired artificial intelligence systems. \nThe dominating memory technologies in the industry have been SRAM\, DRAM (volatile) and NAND flash (non-volatile). Storage class memory (SCM) describes a device category that combines the benefits of solid-state memory with the archival capabilities and low cost per bit of conventional hard disk magnetic storage. In the past decade\, significant focus has been put on the emerging memory technologies that include: MRAM (Magnetic RAM)\, STTRAM (Spin-Transfer Torque RAM)\, FeRAM (Ferroelectric RAM)\, PCRAM (Phase Change RAM)\, RRAM (Resistive RAM) and Memristor. \nThe invention of ferroelectricity in doped hafnium based oxides (HfZrO2\, doped HfO2) has attracted tremendous interest in realizing HfO 2  based devices.  They have large remnant polarization of up to 45 μC cm −2 \, and their coercive field (≈1–2 MV cm −1 ) is larger than conventional ferroelectric films by approximately one order of magnitude. Furthermore\, they can be extremely thin (<10 nm) and have a large bandgap (>5 eV).  The primary devices aimed in these applications are ferroelectric field effect transistors (FeFETs) and ferroelectric tunnel junctions (FTJs).  In FeFETs\, the conventional logic gate dielectric is replaced with a ferroelectric material that remembers the electric field to which it had been exposed resulting in the threshold voltage of two stable binary states similar to the way it is done in a flash memory cell. \nWe are aiming at developing a fabrication platform that will allow fabrication of n and p channel FeFETs and FTJ based circuits using standard CMOS process on 150 mm wafers in a university environment.  We observe FeFETs exhibiting charge trapping and polarization induced memory window. The process developed for fabricating 1T1R FTJ array integrated with NMOS will be described. FTJs are promising candidates for synaptic weight elements in neural network hardware because of their nonvolatile multilevel memory effect. The talk will provide an overview of advances made in various memory technologies with their future trends.
URL:https://seasevents.nmsdev7.com/event/ese-grace-hopper-lecture-santosh-kurinec/
LOCATION:Zoom – Email ESE for Link jbatter@seas.upenn.edu
CATEGORIES:Distinguished Lecture,Faculty,Colloquium,Graduate,Undergraduate
ORGANIZER;CN="Electrical and Systems Engineering":MAILTO:eseevents@seas.upenn.edu
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