ESE PhD Thesis Defense: “Software-like Incremental Refinement on FPGA using Partial Reconfiguration”
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Raisler Lounge (Room 225), Towne Building
220 South 33rd Street, Philadelphia, PA, United States
To improve FPGA design productivity, our goal is to create a development experience for FPGAs that aligns closely with widely accepted software design principles. Software programmers quickly test their minimally completed design, identify the bottleneck, and incrementally refine the design. In FPGA design, however, such incremental refinement is not currently supported. (1) FPGA compilation is long, […]

