Human brains demonstrate how simple computational primitives can be combined in massively parallel ways to produce networks capable of identifying complicated patterns in sensory data. In contrast, electronic computers adopt hardware architectures that process information serially, leading to higher latency and power consumption when implementing intrinsically parallel algorithms, such as neural networks. This software-hardware architectural mismatch has acquired greater attention due to the widespread adoption of large neural networks and has encouraged the prospect of specialized neuromorphic computers. There is great interest in low latency analog neuromorphic designs that utilize passive crossbar arrays to accomplish the dual tasks of storing synaptic weights and computing dot products. Although this compute-in-memory paradigm promises high circuit density and 3D integrability, prevalent implementations combine them with crossbar-incompatible CMOS neurons, a paring that impedes overall system scalability. This thesis addresses the scalability bottleneck by evolving fully crossbar – compatible neuromorphic architectures based on passive circuit embodiments of neuron and synapses.

We demonstrate via SPICE circuit simulations how a shallow network of diode-resistor based passive neurons and resistive voltage summers, despite its inherent inability to buffer, amplify and invert signals, can recognize MNIST digits with 95.4% accuracy. We introduce weight-to-conductance mappings that enable resource-efficient implementation of negative weights. The performance impacts of nanoscale defects are evaluated and methods to boost fault-tolerance are proposed. Compared with conventional implementations, we find all-passive neuromorphic hardware promise higher speed, smaller footprints, and improved vertical scalability.